1. Technical Field
The embodiments described herein relate to semiconductor memory apparatus and, more particularly, to circuits and methods for controlling an activation of a redundancy word line in a semiconductor memory apparatus.
2. Related Art
Generally, when a semiconductor memory apparatus has a few, or even just one defective memory cell, the memory apparatus will not be able to perform the necessary storage operations, and will be regarded as a bad product. Accordingly, redundancy technology, which uses supplementary memory cells in place of defective cells, has been employed in conventional semiconductor memory apparatus.
In conventional apparatus, after the completion of the wafer fabricating processes, a device test is carried out and repair of defective memory cells is performed through fuse cutting. In other words, to provide defect relief, a redundancy circuit containing fuses that can, e.g., be melted using a high-energy light such as laser, is manufactured together with the memory cell and circuit devices of the semiconductor memory apparatus. The address information associated with the defective memory cell, that is, address information for the fuse cutting can be stored and the defective memory cells can be replaced with redundant memory cells in a redundancy cell area by fusing the appropriate fuses in the redundancy circuit.
In a conventional memory device, the memory cells are often arrange into blocks, which can be termed sub-array blocks. There can be a redundancy circuit for each sub-array block, such that if there is a defect in one or more of the cells in a particular sub-array, the sub-array block, or certain cells therein can be replaced with redundancy cells under the control of the associated redundancy circuit. Alternatively, an integrated redundancy circuit can be used for multiple sub-array blocks. For example, a conventional redundancy circuit may comprise an address comparator and a discrimination circuit. For example, the address comparator can be dedicated to each sub-array block and can receive fuse address signals for the replacement of memory cells within the associated sub-array block. The external address signals are compared with the fuse address signals in order to allow access the appropriate redundancy cells. When there is a match between the external address and the fuse array signal, then the redundancy wordlines associated with the appropriate redundancy cells are activated allowing access to the redundancy cells.
Referring to FIG. 1, an exemplary discrimination circuit has a plurality of NAND gates 1 to 3 that receive a fuse enable signal FE and a plurality of comparison signals HIT2 to HIT 12, a NOR gate 4 to combine outputs of the plurality of NAND gates 1 to 3 and an inverter 5 to invert an output of the NOR gate 4. A redundancy control signal HITB is generated by the discrimination circuit based on the plurality of the comparison signals HIT2 to HIT12. The defective memory cell is replaced with a redundancy cell based on the results of the address comparison unit and the discrimination circuit. In other words, word lines of the redundancy cell array can be activated or inactivated in accordance with the result of the discrimination performed by the discrimination circuit.
Unfortunately, the access time to the semiconductor memory apparatus can be increased due to the delay time that is required to compare the address signals and perform the discrimination. Particularly, in cases where the discrimination circuit is composed of logic combination circuits having a plurality of series-stages to receive a plurality of signals, as is often the case, the discrimination time is delayed while the signals are transferred through each stage. Further, it is not sufficient to simply operate the circuit at high speed because the redundancy control signal is generated after the comparison signals are received and the turn-on operations are progressively carried out via each stage. The series-stages architecture also brings the added disadvantage that it increases layout area requirements.